Low power consumption is an important requirement in the design of data processing systems. For example many applications such as cell phones, personal digital assistants, and the like are powered by a battery. In order to avoid frequent battery changes or the need to connect the battery to a charger, it is desirable that all integrated circuits consume a minimum amount of power. Modern digital integrated circuit fabrication techniques use complementary metal oxide semiconductor (CMOS) transistors which facilitate low power consumption. CMOS logic circuits only consume significant amounts of power when they are switching and integrated circuits built using CMOS technology, or significant portions thereof, may be designed to operate statically, allowing the power to be reduced during periods of inactivity.
Early power reduction techniques were hardware based. For example in an electronic hand held calculator, the user would enable the arithmetic circuitry by depressing a key. The arithmetic circuitry would input the operands and perform the calculation before shutting down.
However these techniques proved to be inadequate for microprocessors which might, for example, perform periodic functions independent of any user input. U.S. Pat. No. 4,758,945 invented by James J. Remedi discloses two software-based techniques for power reduction. The first technique, known as WAIT mode, causes the clock signals to be interrupted between the oscillator and the data processing system in response to a WAIT instruction. WAIT mode takes advantage of the fact that clock signals provided to a static CMOS microprocessor can be interrupted without the microprocessor losing its state. The second technique is known as STOP mode. In STOP mode, not only are the microprocessor's clock signals interrupted, but the oscillator itself is also disabled. Thus even the power consumed by the oscillator circuit is saved. However exit from STOP mode requires a wake-up delay for the clock signals from the oscillator to stabilize before being driven to the microprocessor and STOP mode cannot be used in situations that require fast response to external events.
Recently the level of integration of functions onto a single integrated circuit has increased. For example there is a new class of integrated circuit known as a system-on-chip (SOC). SOCs incorporate a central processing unit (CPU), memory, and various I/O peripherals onto a single semiconductor chip. Many of the I/O peripherals are themselves complex and may be bus masters. For devices of this complexity, software control is no longer adequate. Software control assumes that the CPU is able to determine through the flow of software itself the occurrence of periods of activity and inactivity. However in complex SOCs, events requiring operation of the peripherals and the system bus occur indeterminately with respect to the flow of software on the CPU. Furthermore in such SOCs the percentage of chip area devoted to the CPU is relatively small, and the amount of power reduction that can be achieved by the CPU going into WAIT mode or STOP mode alone is not sufficient.
Thus a new method for power reduction that is not limited to the CPU and that does not rely on the flow of software running on the CPU would be desirable. Such a method and a data processing system using it are provided by the present invention, whose features and advantages will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.